Electronic technologies such as digital computers, calculators, audio devices, video equipment and telephone systems have facilitated increased productivity and reduced costs in a number of activities, including the analysis and communication of data, ideas and trends in most areas of business, science, education, and entertainment. There are a number of different complex electronic Application Specific Integrated Circuits (ASICs) that have contributed to the realization of these benefits. Design of ASICs often involves the design of various building block circuits that make up the ASIC. Significant resources are usually expended performing the design tasks associated with designing connection between building block circuits and adding the necessary support logic to complete a system on a chip (SoC), such as adding input/output (I/O) cells, clock distribution and test logic. After a design is complete, even more resources are typically expended verifying the operation via simulation.
Designing complex electronic systems and circuits requires arduous analysis of numerous electrical characteristics, including the performance of extensive calculations and manipulation of complicated electrical principles of physics. Typically an analysis becomes even more complex when designers attempt to integrate numerous electronic components on a single integrated circuit chip, giving rise to a variety of factors requiring careful review and attention. Engineers regularly rely on computer aided engineering (CAE) design tools to assist with many of the complicated manipulations, computations and analyses that are required to design electronic circuits, especially when a large part of the design is included in an integrated chip. Circuits being designed or analyzed usually include resistors, capacitors, inductors, voltage and current sources, switches, uniform distributed RC lines, and common semiconductor devices such as bipolar junction transistors (BJT), junction field effect transistors (JFET), metal oxide surface field effect transistors (MOSFET), etc. A good analysis typically involves a review of numerous electrical characteristics associated with each component.
Many CAE tools utilize netlists of hardware description language (HDL) files to describe the architectural and functional characteristics of a design. HDL files are usually textual descriptions of the logical functions a circuit performs. The textual descriptions are utilized in a synthesis process that turns the conceptual textual description of the design into a “logical gate” description. For example register transfer level (RTL) functional description file with an implied architecture is translated into a gate level description. Even after a CAE design is completed significant resources are expended verifying the design in silicon.
IC chips typically include various functional circuit blocks that are coupled together and to Input/Output (IO) cells. Through design reuse, significant advantages are usually achieved through “reuse” of basic building block circuits that have been previously verified in silicon. Although the internal design of the previously verified building block circuits does not significantly change, they usually are required to exhibit different behavior in different applications and typically have significantly distinct interfaces from one application to another. Coupling the HDL descriptions of different functional circuit blocks together, generating HDL descriptions of inputs and outputs (IOs) based on the choice of interfaces, adding system level logic for clocking and testing, generating a test bench and the tests to verify the functionality and connectivity of an IC are typically tedious tasks consuming significant resources. In addition, these design and test activities associated with coupling the different HDL descriptions of functional circuit blocks together are error prone, especially when manual intervention or complex coordination is required.
Valuable experience and information associated with previous design and actual manufacturing of electronic systems is often not available to new design teams. Typically new designs are generated by teams of engineers that do not include engineers that participated in the original design of a circuit block. The new teams of engineers often do not know the circuit block was previously designed, manufactured, tested and debugged and perform these tasks them selves. Even if the new team includes engineers with experience designing and manufacturing a circuit block, remembering previous designs and circuit block descriptions is often difficult.
Accordingly, what is required is a system and method that facilitates efficient creation of IC netlist designs utilizing existing circuit block information. The system and method should assist a designer to design an IC netlist in a convenient manner and facilitate incorporation of building block circuits previously tested in silicon. The system and method should reduce the amount of data a user has to enter manually to adequately describe features of the circuit being designed or analyzed.